Renesas Electronics /R7FA6T2BD /SCI_B0 /TDR

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Interpret as TDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TDAT0 (0)MPBT 0 (0)TSYNC

MPBT=0, TSYNC=0

Description

Transmit Data Register

Fields

TDAT

Serial transmit data

MPBT

Multi-processor transfer bit flag

0 (0): Data transmission cycles

1 (1): ID transmission cycles

TSYNC

Transmit SYNC data

0 (0): The Start Bit is transmitted as DATA SYNC.

1 (1): The Start Bit is transmitted as COMMAND SYNC.

Links

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